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Thread: electron microscope scans of TSMC vs Intel chips

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    electron microscope scans of TSMC vs Intel chips


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    JamesWasil (25th September 2020)

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    That was a really good video. Thanks for sharing that. I kind of figured that they were using the nomenclature for marketing rather than really at the level of nm design they were saying after the early 2000's. This really put it into perspective with great detail.

    It's probably best to use the transistor count present as a gauge to know if it is or isn't more compact than a predecessor even with new technologies that are ahead of extreme ultraviolet lithography.

    You may have already seen this link, but if not there is a good suggestion for that here, where they suggest using a combination of characteristics to make it more accurate again: https://spectrum.ieee.org/semiconduc...semiconductors

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    It is funny that he is not measuring gate length. You need to look from above to measure gate length (L) . He is measuring something closer to gate width. Also notice that a transistor can have multiple fins to drop Rds and increase Ids.

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    For quite some time Intel doesn't (like to) provide transistor counts. Here are some numbers for their 14nm process:
    https://en.wikichip.org/wiki/intel/m...l_(client)#Die
    - Dual-core, 1,300,000,000 transistors, 82 mm² die size = 15.9 MTr/mm^2
    - Dual-core Broadwell with Iris Pro die, 1,900,000,000 transistors, 133 mm2 die size = 14.3 MTr/mm^2
    - Deca-core Broadwell, 3,400,000,000 transistors, 246 mm2 die size = 13.8 MTr/mm^2
    https://en.wikichip.org/wiki/intel/m...e_(client)#Die
    - dual-core GT2 Skylake, ~1,750,000,000 transistors, ~101.83 mm² die size = 17.2 MTr/mm^2

    Pretty small number for transistor density(MTr/mm^2), but that's understandable as any complex ASIC is made of different types of circuitry and transistor density depends on that type, e.g. caches are most dense, logic is medium density, analog is lowest density. The original Intel 14nm process was rated for about 40 MTr/mm^2, Intel 14nm with pluses were less dense, rated somewhat above 30 MTr/mm^2.

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    Quote Originally Posted by Piotr Tarsa View Post
    For quite some time Intel doesn't (like to) provide transistor counts. Here are some numbers for their 14nm process:
    https://en.wikichip.org/wiki/intel/m...l_(client)#Die
    - Dual-core, 1,300,000,000 transistors, 82 mm² die size = 15.9 MTr/mm^2
    - Dual-core Broadwell with Iris Pro die, 1,900,000,000 transistors, 133 mm2 die size = 14.3 MTr/mm^2
    - Deca-core Broadwell, 3,400,000,000 transistors, 246 mm2 die size = 13.8 MTr/mm^2
    https://en.wikichip.org/wiki/intel/m...e_(client)#Die
    - dual-core GT2 Skylake, ~1,750,000,000 transistors, ~101.83 mm² die size = 17.2 MTr/mm^2

    Pretty small number for transistor density(MTr/mm^2), but that's understandable as any complex ASIC is made of different types of circuitry and transistor density depends on that type, e.g. caches are most dense, logic is medium density, analog is lowest density. The original Intel 14nm process was rated for about 40 MTr/mm^2, Intel 14nm with pluses were less dense, rated somewhat above 30 MTr/mm^2.
    Yes because they use high performance standard cells to get higher clock frequency. They use transistors with higher number of fins.
    Also look at https://www.realworldtech.com/transi...flawed-metric/

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